In a multi-level memory device cells generally assume more than two logic states and thus may store information of more than one bit. A multi-level memory device that occupies a silicon area slightly larger than that of a four-level memory device of the same storage capacity is described in the Italian patent application VA2006A000065, assigned to the current assignee. It employs three-level cells whereby each pair of cells is to store a string of three bits and comprises a coding circuit and a decoding circuit for converting, in a write operation, the strings of three bits to be stored, in strings of two ternary values to be written in respective pairs of three-level cells, and vice versa during a read operation.
There may be three possible states of each cell, thus the relative distributions of the three different read thresholds can be relatively farther away from the voltage levels at which the known “read disturb” and “retention” phenomena (discussed in the above cited prior Italian patent application) are more severe.
A method of managing a multi-level memory device that addresses the issues caused by an accidental interruption or supply voltage drop of a magnitude capable of stopping an ongoing program operation that could take place during programming and that may render the memory device usable as if it were a two-bit memory device, is also disclosed in the above cited prior Italian patent application.
According to the three-level memory device disclosed in the prior application, each cell may assume one of three possible logic values, with the advantage of an area occupation significantly smaller than that of a common one-bit-per-cell memory device, though with a reduced number of threshold voltage distributions than a two-bit-per-cell memory device. This may make unnecessary error correction code techniques, that may otherwise be indispensable with present day technology two-bit per cell devices for ensuring an acceptable reliability, and thus the consequent limitations in terms of “bit manipulation” that the use of ECC technique may impose.
An architecture of the memory device according to the cited prior application is schematically depicted in FIG. 1.